hlslib: Software Engineering for Hardware Design

Johannes de Fine Licht, Torsten Hoefler
10/10/2019
cs.ARcs.DCcs.SE

Official code: definelicht/hlslib (342 stars, BSD-3-Clause, last commit 2025-01-20).

Abstract

High-level synthesis (HLS) tools have brought FPGA development into the mainstream, by allowing programmers to design architectures using familiar languages such as C, C++, and OpenCL. While the move to these languages has brought significant benefits, many aspects of traditional software engineering are still unsupported, or not exploited by developers in practice. Furthermore, designing reconfigurable architectures requires support for hardware constructs, such as FIFOs and shift registers, that are not native to CPU-oriented languages. To address this gap, we have developed hlslib, a collection of software tools, plug-in hardware modules, and code samples, designed to enhance the productivity of HLS developers. The goal of hlslib is two-fold: first, create a community-driven arena of bleeding edge development, which can move quicker, and provides more powerful abstractions than what is provided by vendors; and second, collect a wide range of example codes, both minimal proofs of concept, and larger, real-world applications, that can be reused directly or inspire other work. hlslib is offered as an open source library, containing CMake files, C++ headers, convenience scripts, and examples codes, and is receptive to any contribution that can benefit HLS developers, through general functionality or examples.

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Code Implementations(1)

definelicht/hlslibOfficial100%
BSD-3-Clause

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

34260C, C++Feb 21, 20181 years agoBSD-3-Clause
cmakefpgahigh-level-synthesishpcintel-fpga+5 more

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Cite this paper

@article{licht2019hlslib,
  title  = {hlslib: Software Engineering for Hardware Design},
  author = {Johannes de Fine Licht and Torsten Hoefler},
  year   = {2019},
  eprint = {1910.04436},
  archivePrefix = {arXiv},
  url    = {https://arxiv.org/abs/1910.04436}
}

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