Real-Time FPGA Demonstrator of ANN-Based Equalization for Optical Communications

Jonas Ney, Patrick Matalla, Vincent Lauinger, Laurent Schmalen, Sebastian Randel +1 more
2/23/2024
eess.SPcs.LG

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Abstract

In this work, we present a high-throughput field programmable gate array (FPGA) demonstrator of an artificial neural network (ANN)-based equalizer. The equalization is performed and illustrated in real-time for a 30 GBd, two-level pulse amplitude modulation (PAM2) optical communication system.

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Cite this paper

@article{ney2024realtime,
  title  = {Real-Time FPGA Demonstrator of ANN-Based Equalization for Optical Communications},
  author = {Jonas Ney and Patrick Matalla and Vincent Lauinger and Laurent Schmalen and Sebastian Randel and Norbert Wehn},
  year   = {2024},
  eprint = {2402.15288},
  archivePrefix = {arXiv},
  url    = {http://arxiv.org/abs/2402.15288v1}
}

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