HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design

Jinwei Tang, Jiayin Qin, Kiran Thorat, Chen Zhu-Tian, Yu Cao +3 more
12/6/2024
cs.LGcs.AIcs.AR

No official code found. Best implementation: SazzadSowmik/HiVeGen-Pipeline-Reproduction (1 star, last commit 2025-11-18).

Abstract

With Large Language Models (LLMs) recently demonstrating impressive proficiency in code generation, it is promising to extend their abilities to Hardware Description Language (HDL). However, LLMs tend to generate single HDL code blocks rather than hierarchical structures for hardware designs, leading to hallucinations, particularly in complex designs like Domain-Specific Accelerators (DSAs). To address this, we propose HiVeGen, a hierarchical LLM-based Verilog generation framework that decomposes generation tasks into LLM-manageable hierarchical submodules. HiVeGen further harnesses the advantages of such hierarchical structures by integrating automatic Design Space Exploration (DSE) into hierarchy-aware prompt generation, introducing weight-based retrieval to enhance code reuse, and enabling real-time human-computer interaction to lower error-correction cost, significantly improving the quality of generated designs.

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Code Implementations(1)

SazzadSowmik/HiVeGen-Pipeline-ReproductionCommunity58%

Reproduction of the HiVeGen (Hierarchical LLM-based Verilog Generation) pipeline from the paper "HiVeGen – Hierarchical LLM-based Verilog Generation for Scalable Chip Design" (arXiv:2412.05393).

11C, C++Oct 27, 202511 months ago
demo-paper-implementationhardware-designshdlhierachicalhierachical-structure+10 more

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Cite this paper

@article{tang2024hivegen,
  title  = {HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design},
  author = {Jinwei Tang and Jiayin Qin and Kiran Thorat and Chen Zhu-Tian and Yu Cao and Yang and Zhao and Caiwen Ding},
  year   = {2024},
  eprint = {2412.05393},
  archivePrefix = {arXiv},
  url    = {http://arxiv.org/abs/2412.05393v2}
}

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