VUSA: Virtually Upscaled Systolic Array Architecture to Exploit Unstructured Sparsity in AI Acceleration

Shereef Helal, Alberto Garcia-Ortiz, Lennart Bamberg
6/1/2025
cs.ARcs.AIcs.LG

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Abstract

Leveraging high degrees of unstructured sparsity is a promising approach to enhance the efficiency of deep neural network DNN accelerators - particularly important for emerging Edge-AI applications. We introduce VUSA, a systolic-array architecture that virtually grows based on the present sparsity to perform larger matrix multiplications with the same number of physical multiply-accumulate MAC units. The proposed architecture achieves saving by 37% and 68% in area and power efficiency, respectively, at the same peak-performance, compared to a baseline systolic array architecture in a commercial 16-nm technology. Still, the proposed architecture supports acceleration for any DNN with any sparsity - even no sparsity at all. Thus, the proposed architecture is application-independent, making it viable for general-purpose AI acceleration.

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Cite this paper

@article{helal2025vusa,
  title  = {VUSA: Virtually Upscaled Systolic Array Architecture to Exploit Unstructured Sparsity in AI Acceleration},
  author = {Shereef Helal and Alberto Garcia-Ortiz and Lennart Bamberg},
  year   = {2025},
  eprint = {2506.01166},
  archivePrefix = {arXiv},
  url    = {http://arxiv.org/abs/2506.01166v1}
}

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