VeriLocc: End-to-End Cross-Architecture Register Allocation via LLM

Lesheng Jin, Zhenyuan Ruan, Haohui Mai, Jingbo Shang
6/20/2025
cs.CLcs.OS

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Abstract

Modern GPUs evolve rapidly, yet production compilers still rely on hand-crafted register allocation heuristics that require substantial re-tuning for each hardware generation. We introduce VeriLocc, a framework that combines large language models (LLMs) with formal compiler techniques to enable generalizable and verifiable register allocation across GPU architectures. VeriLocc fine-tunes an LLM to translate intermediate representations (MIRs) into target-specific register assignments, aided by static analysis for cross-architecture normalization and generalization and a verifier-guided regeneration loop to ensure correctness. Evaluated on matrix multiplication (GEMM) and multi-head attention (MHA), VeriLocc achieves 85-99% single-shot accuracy and near-100% pass@100. Case study shows that VeriLocc discovers more performant assignments than expert-tuned libraries, outperforming rocBLAS by over 10% in runtime.

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Cite this paper

@article{jin2025verilocc,
  title  = {VeriLocc: End-to-End Cross-Architecture Register Allocation via LLM},
  author = {Lesheng Jin and Zhenyuan Ruan and Haohui Mai and Jingbo Shang},
  year   = {2025},
  eprint = {2506.17506},
  archivePrefix = {arXiv},
  url    = {http://arxiv.org/abs/2506.17506v1}
}

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